Synopsys IP Technical Bulletin: USB High Speed Inter-Chip (HSIC) IP: What is it? And why should I use it?
USB v2.0 Soft PHY and Device Controller
High Speed Inter-CHIP USB 2.0 PHY | Arasan Chip Systems
Figure 2 from Verilog synthesis of USB 2.0 full-speed device PHY IP | Semantic Scholar
USB3250 | Microchip Technology
The Next-Generation Interconnect | Mouser
Teledyne LeCroy - USB and USB Type-C® Electrical Test Solutions
USB3 Controller | Cadence
USB 2.0 PHY IP core | Arasan Chip Systems
Soft Mixed Signal Corporation USB 2.0 PHY IP Cores
USB2.0 PHY – Silicon Library Inc.
Archimago's Musings: MEASUREMENTS: Computer USB port noise, USB hubs and the 8kHz PHY Microframe Packet Noise
XPS USB 2.0 Host Controller
USBPHYC internal peripheral - stm32mpu
Low Power USB 2.0 PHY IP for High-Volume Consumer Applications
USB Universal Serial Bus
Figure 1 from Verilog synthesis of USB 2.0 full-speed device PHY IP | Semantic Scholar
PCIe/USB/SATA PHY Application Example | Renesas
Mixed-Signal Verification for USB 2.0 Physical Layer IP
Canovatech - CT25201
TUSB1210-Q1 data sheet, product information and support | TI.com
PhyWhisperer-USB | Crowd Supply
USB 2.0 Full High Speed Solution | NXP Semiconductors
TUSB1210 data sheet, product information and support | TI.com
Webcam - Encore Electronics Inc.
USB2 Controller | Cadence
